1. Field of the Invention
The present invention generally relates to methods for measuring the misalignment, or overlay error, between the patterns created on a wafer in different steps of the integrated circuit manufacturing process, and more specifically to improved methods of measuring misalignment which utilize geometric phase analysis.
2. Description of the Related Art
During the process of integrated circuit fabrication, several hundred processing steps may be required as thin layers of semiconductors, insulators and metals are deposited and patterned. The patterns in each layer of the integrated circuit are created using the process of lithography. A photosensitive resist (xe2x80x9cphotoresistxe2x80x9d) is deposited on the silicon wafer and exposed to light through a mask carrying the desired pattern. The photoresist is then developed and removed from areas corresponding to the pattern, allowing the pattern to be transferred by etching into the layer below.
With every generation of smaller and faster integrated circuits, the size of features in the masks is reduced, and the accuracy with which features in each layer must be aligned with those formed in previous layers must increase. Therefore, the problem of measuring the misalignment between features formed in different layers has become more critical. State of the art 64 Mb dynamic random access memory (DRAM) chips contain circuits with features as small as 250 nanometers (nm), and performance of the circuit is affected if one set of features is misaligned by more than about 10 nm from the set of features formed in previous processing steps. The placement precision, or cumulative difference between patterns from various mask levels, is commonly called xe2x80x9coverlay errorxe2x80x9d.
To measure the amount of misalignment, or overlay error, the industry currently makes use of an alignment technique illustrated in FIGS. 1A and 1B. Each mask includes several alignment areas, separate from the wiring or other pattern of the circuit. These alignment areas contain alignment marks which are cross-shaped or chevron-shaped features, usually several microns in length. FIG. 1A shows a plan view of such an alignment area.
The first alignment mark is etched onto the wafer at the first mask level (referred to hereafter as level xe2x80x9cAxe2x80x9d) and subsequent levels are aligned with respect to this mark. In the example illustrated here, the alignment mark for level xe2x80x9cAxe2x80x9d consists of four large chevrons (labeled xe2x80x9c10xe2x80x9d in FIG. 1A) arranged at the corners of a 50xc3x9750 micron square. After level xe2x80x9cAxe2x80x9d is patterned using the mask, the chevrons are easily visible in an optical microscope. The next mask (referred to as level xe2x80x9cBxe2x80x9d) is then exposed. Level xe2x80x9cBxe2x80x9d has a smaller set of chevrons (labeled 11) which, if accurately aligned, will fit within the larger chevrons of level xe2x80x9cAxe2x80x9d. After exposure and development of the photoresist for level xe2x80x9cBxe2x80x9d, the alignment mark for level xe2x80x9cBxe2x80x9d is faintly visible in the photoresist. By measuring the positions of the edges of the chevrons along a line L-Lxe2x80x2, as shown in FIG. 1B, the degree of misalignment (labeled 12 in FIG. 1B) in the x direction can be measured. A similar measurement is then done in the y direction. If the error is beyond acceptable tolerances, the photoresist is washed off and the exposure of the level B mask is repeated.
This technique was originally developed for much larger feature sizes, but after several years of optimization this technique is now being used to measure overlay error with an accuracy of 10 nm. This accuracy is sufficient for present day needs but will be inadequate for future generations of integrated circuits with smaller feature sizes requiring more precise alignment. For these smaller circuits, yield problems occur when the conventional technique measures an acceptable overlay error and allows the wafer to be fully processed, but it is later found that there is poor performance due to an overlay error smaller than can be resolved using the technique.
A separate problem of the conventional technique is that it relies on measurements of large alignment marks, several microns in size, whereas the features in the actual circuits are much smaller, of the order of 250 nm (or 0.25 microns). Large alignment marks are used because they are visible in an optical microscope and therefore can easily be measured: the optical microscope can resolve features down to about 250 nm. However, since the processing is optimized for the smaller features in the circuit, the edges of the large alignment marks may be improperly etched, making it difficult to measure their positions. More importantly, it may be difficult to relate the position of the large alignment marks to the positions of the small features in the actual circuits, because large and small features are etched at different rates during processing.
To improve measurement accuracy, and to avoid the problems associated with using large alignment marks, several other overlay measurement techniques have been suggested, such as techniques based on moire fringes. In moire fringe techniques, the alignment marks are large areas filled with a regular pattern of small lines or dots.
In a typical example of a moire fringe technique, an alignment mark consisting of a regular pattern of dots is etched onto the wafer at the first mask level (again referred to as level xe2x80x9cAxe2x80x9d). The next mask level xe2x80x9cBxe2x80x9d is then exposed. The alignment mark for level xe2x80x9cBxe2x80x9d also consists of a regular pattern of dots and these are superimposed over the level xe2x80x9cAxe2x80x9d pattern. However, the level xe2x80x9cBxe2x80x9d pattern has a slightly different spacing between dots. Because of this difference in spacing, in some places the xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d dots are in registry, i.e. superimposed exactly, but in other places they are out of registry. Although individual dots are too small to see clearly in an optical microscope, the areas where dots are in and out of registry (the xe2x80x9cmoirxc3xa9 fringesxe2x80x9d) can be distinguished optically. Visual inspection of the position of these areas is used to determine the overlay error.
By using alignment marks which are made up of many small dots or lines, moirxc3xa9 fringe techniques avoid the problems associated with using large features for alignment marks. However, other significant problems occur with moirxc3xa9 fringe techniques. Three problems are worth noting. Firstly, once the level xe2x80x9cAxe2x80x9d pattern of dots is etched onto the wafer, it forms a non-planar surface on which the level xe2x80x9cBxe2x80x9d pattern must be placed. This can distort the level xe2x80x9cBxe2x80x9d pattern and make it difficult to expose and develop correctly. A second problem is that the level xe2x80x9cBxe2x80x9d pattern shows very weak contrast (since it is only patterned in photoresist) compared to level xe2x80x9cAxe2x80x9d (which is etched onto the wafer). When superimposed onto the high contrast level xe2x80x9cAxe2x80x9d pattern, level xe2x80x9cBxe2x80x9d is very difficult to see, making the moirxc3xa9 fringes weak and the measurement less precise. A third problem is that the difference in spacing between levels xe2x80x9cAxe2x80x9d and xe2x80x9cBxe2x80x9d must be small (around 1%) and carefully controlled in order to get appropriate moirxc3xa9 fringes and this can be difficult to achieve.
The invention to be described below is significantly different from both the moirxc3xa9 and conventional techniques which have just been described, in that it uses a different type of alignment mark combined with mathematical analysis to measure the overlay error. This enables the problems described above to be avoided while also allowing an improved accuracy in the measurement of overlay error.
The object of the present invention is to provide a structure and method for measuring the overlay error between at least two mask levels, each of which includes specific alignment marks. These alignment marks consist of repeating patterns of small dots or other features. All marks have the same spacing between features, and alignment marks from successive mask levels are placed next to each other. Mathematical analysis of the aligmnent marks is then used to calculate the overlay error with a high degree of accuracy. For this, the invention makes use of mathematical techniques for the analysis of periodically repeating patterns, such as geometric phase analysis and other techniques involving Fourier transforms.
More specifically, the invention comprises a method of measuring overlay error comprising forming a first mask having a first alignment array comprising a periodic pattern of first features having a first periodicity, forming a second mask having a second alignment array comprising a pattern of second features having the first periodicity, the first alignment array being adjacent the second alignment array, the first alignment array and the second alignment array forming a combined alignment array, transforming the combined alignment array to produce a transformed array, selecting a first region within the transformed array, inverse transforming the region to produce geometric phase shift information, averaging the phase shift information, converting the averaged phase shift information into a value for misalignment in a first direction corresponding to the first region, repeating the above steps using a second region within the transformed array to calculate a value for misalignment in a second direction corresponding to the second region, calculating an overlay error between the first and second mask levels by adding the components of misalignment in the first direction and second direction. The transforming step comprises calculating a Fourier transform and the inverse transforming step comprises calculating an Inverse Fourier transform.
The invention can be used for accurate measurement of the overlay error between mask layers during the fabrication of circuits with a small feature sizes of around 250 nm and below. The invention is significantly different from, and has advantages over, both conventional and moirxc3xa9 techniques for overlay measurement. Overlay error is measured with an accuracy of better than 2.5 nm, an improvement of at least four times over the accuracy achieved using conventional techniques, and the invention avoids the problems which have already been described for conventional and moirxc3xa9 techniques.